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mirror of https://github.com/wolfpld/tracy.git synced 2025-03-20 07:40:02 +08:00

Check if ring buffer was properly mapped.

This commit is contained in:
Bartosz Taudul
2022-04-04 17:56:40 +02:00
parent 2b24ad27b2
commit 3d28d1259b
+27
View File
@@ -861,9 +861,12 @@ bool SysTraceStart( int64_t& samplingPeriod )
TracyDebug( " No access to kernel samples\n" );
}
new( s_ring+s_numBuffers ) RingBuffer( 64*1024, fd, EventCallstack );
if( s_ring[s_numBuffers].IsValid() )
{
s_numBuffers++;
TracyDebug( " Core %i ok\n", i );
}
}
// CPU cycles + instructions retired
pe = {};
@@ -892,10 +895,13 @@ bool SysTraceStart( int64_t& samplingPeriod )
if( fd != -1 )
{
new( s_ring+s_numBuffers ) RingBuffer( 64*1024, fd, EventCpuCycles );
if( s_ring[s_numBuffers].IsValid() )
{
s_numBuffers++;
TracyDebug( " Core %i ok\n", i );
}
}
}
pe.config = PERF_COUNT_HW_INSTRUCTIONS;
for( int i=0; i<s_numCpus; i++ )
@@ -904,11 +910,14 @@ bool SysTraceStart( int64_t& samplingPeriod )
if( fd != -1 )
{
new( s_ring+s_numBuffers ) RingBuffer( 64*1024, fd, EventInstructionsRetired );
if( s_ring[s_numBuffers].IsValid() )
{
s_numBuffers++;
TracyDebug( " Core %i ok\n", i );
}
}
}
}
// cache reference + miss
if( !noCache )
@@ -926,10 +935,13 @@ bool SysTraceStart( int64_t& samplingPeriod )
if( fd != -1 )
{
new( s_ring+s_numBuffers ) RingBuffer( 64*1024, fd, EventCacheReference );
if( s_ring[s_numBuffers].IsValid() )
{
s_numBuffers++;
TracyDebug( " Core %i ok\n", i );
}
}
}
pe.config = PERF_COUNT_HW_CACHE_MISSES;
for( int i=0; i<s_numCpus; i++ )
@@ -938,11 +950,14 @@ bool SysTraceStart( int64_t& samplingPeriod )
if( fd != -1 )
{
new( s_ring+s_numBuffers ) RingBuffer( 64*1024, fd, EventCacheMiss );
if( s_ring[s_numBuffers].IsValid() )
{
s_numBuffers++;
TracyDebug( " Core %i ok\n", i );
}
}
}
}
// branch retired + miss
if( !noBranch )
@@ -955,10 +970,13 @@ bool SysTraceStart( int64_t& samplingPeriod )
if( fd != -1 )
{
new( s_ring+s_numBuffers ) RingBuffer( 64*1024, fd, EventBranchRetired );
if( s_ring[s_numBuffers].IsValid() )
{
s_numBuffers++;
TracyDebug( " Core %i ok\n", i );
}
}
}
pe.config = PERF_COUNT_HW_BRANCH_MISSES;
for( int i=0; i<s_numCpus; i++ )
@@ -967,11 +985,14 @@ bool SysTraceStart( int64_t& samplingPeriod )
if( fd != -1 )
{
new( s_ring+s_numBuffers ) RingBuffer( 64*1024, fd, EventBranchMiss );
if( s_ring[s_numBuffers].IsValid() )
{
s_numBuffers++;
TracyDebug( " Core %i ok\n", i );
}
}
}
}
s_ctxBufferIdx = s_numBuffers;
@@ -1001,10 +1022,13 @@ bool SysTraceStart( int64_t& samplingPeriod )
if( fd != -1 )
{
new( s_ring+s_numBuffers ) RingBuffer( 256*1024, fd, EventContextSwitch, i );
if( s_ring[s_numBuffers].IsValid() )
{
s_numBuffers++;
TracyDebug( " Core %i ok\n", i );
}
}
}
if( wakeupId != -1 )
{
@@ -1018,12 +1042,15 @@ bool SysTraceStart( int64_t& samplingPeriod )
if( fd != -1 )
{
new( s_ring+s_numBuffers ) RingBuffer( 64*1024, fd, EventWakeup, i );
if( s_ring[s_numBuffers].IsValid() )
{
s_numBuffers++;
TracyDebug( " Core %i ok\n", i );
}
}
}
}
}
TracyDebug( "Ringbuffers in use: %i\n", s_numBuffers );